Santa Clara, CA, USA
1. Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
2. Contribute significantly to verification infrastructure development. This includes verification test bench construction and creation of reference models in high description languages (C, System-Verilog, System-C)
3. Development of System Verilog/UVM based on test plan from functional requirements
4. Maintain regression list and run regression tests to make sure the design works correctly
1. Master degree desired, Bachelor's degree in CS/EE is required. 3+ years of relevant experience in ASIC verification field
2. Will be responsible for definition, development and execution of self-checking tests for complex digital ASICs
3. Should have worked on developing/implementing test plans at the chip-level for complex ASICs. • Fluent in System Verilog and scripting languages such as Python or Perl
4. Must have intimate knowledge of UVM methodology. • Experience in the verification of SoC and other IPs such as CPU Subsystem, Ethernet, PCIE, DDR, Serdes etc
5. Knowledgeable about assertions and functional coverage
6. Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies
7. Very good communication skills and ability and desire to work in a geographically diverse team environment