PRINCIPAL SOC DESIGN ENGINEER

LOCATION:

Santa Clara, CA, USA

RESPONSIBILITIES:

1. Work with software and hardware engineering groups to design AI accelerator and SoC

2. Write detail specifications and define micro-architecture of the design

3. Implement high performance design using high-quality RTL coding techniques

4. Work with performance modeling/analysis team to enhance the performance

5. Collaborate with the verification team on the verification test plan, coverage analysis, and full-chip simulation plus debug

6. Work with the physical design team in aiding the implementation of the functional blocks

7. Work with multiple design groups to shape future design

8. Support the post silicon team to bring up silicon in the lab

9. Work with the software team to ensure product meets customer use cases

1. BS/MS in Electronics Engineering with minimum of 3 years of RTL design experiences

2. Strong Verilog/SystemVerilog RTL coding skill

3. Experience in Micro Architecture/Resoruce tradeoff, SoC Integration, CDC, LINT

4. Experience with performing synthesis, timing analysis/timing closure, formal verification/LEC, DFT Design expertise

5. Hands on experience in AI chip design is a good plus

6. Knowledge with CPU/GPU/DSP/AI Accelerator Architecture Design

7. Familiarity with revision control concepts and tools (e.g. GIT)