ASIC/FPGA Design Engineer
Location:
Silicon Valley, Shenzhen or Shanghai
Your Responsibilities:
1. You will work with the hardware and software teams to design an ASIC/FPGA system for CNN accelerate engine.
2. Design the micro-architecture and protocols to meet the system performance requirements.
3. Write the RTL for multiple blocks according to design specification.
4. Work with verification team to test/debug the design.
5. Bring up and validate the design in the lab.
Qualification:
1. 5+ years relevant experience of ASIC/FPGA design.
2. Experience with the latest industry ASIC/FPGA development tools, design flow and verification methodology
3. Working knowledge with implementing ASIC/FPGA designs using industry standard FPGA development languages, such as Verilog and System Verilog.
4. Familiar with ARM processor, DDR controller, AMBA protocol and PCIE interface.
5. Ability to work effectively in a team
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