Santa Clara, CA, USA
1. Responsible for SoC system functions and feasibility analysis of AI chips
2. Responsible for AI chip software and hardware function partition and SoC system architecture spec
3. Responsible for the detailed design of AI SoC chip including address space partition, chip interface and timing
4. Develop system emulators through languages such as C++/SystemC/Python and evaluate the performance of the AI SoC chip system, and propose design improvement
5. Write up architecture and microarchitecture documents and collaborate with RTL design and verification engineers
6. Work closely with other architects/hardware and software engineers for implementation, integration, and test plan development and execution
1. Possess a Master's, PhD in EE/CS/CE or more than 6 years of relevant professional experience with successful complex chip tape-out experience
2. Experience in designing complex SoC systems such as CPU/GPU/AI chips
3. Experience with SoC bus (AXI/APB), NoC, video codec, CPU, GPU, host interface (PCIe) and memory technology (DDR)
4. Experience with VLSI design and verification, especially in power optimization methodologies
5. Strong working knowledge of ASIC design flow from RTL design to backend implementation
6. C/C++, Python scripting and Verilog design experience
7. Excellent written and oral communication, excellent organizational skills and high self-motivation