1. Work with RTL designers for ASIC/FPGA system verification.
2. Develop detailed coverage plans and test bench, test cases based on the specification.
3. Manage regressions, gather coverage, and debug failed cases.
1. BS or MS in Computer Science or Electrical Engineering.
2. 5+ years relevant experience of ASIC/FPGA design.
3. Good knowledge of System Verilog/UVM testbench language.
4. Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations.
5. Ability to work effectively in a teamSEND RESUMe